The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a SOI wafer having a device formation layer of a planar surface.
In general, a silicon-on-insulator ("SOI") wafer has advantages of complete isolation, low parasitic capacitance and high speed performance. Such a SOI wafer comprises a base substrate, a Si substrate on which the device is formed (Hereinafter, refer to a device substrate), and an insulator formed between the aforementioned substrates.
There are two methods for the fabrication of the SOI wafer, a separation by implated oxygen("SIMOX") method and a bonding method. The SIMOX method implants oxygen ions into a Si substrate to form SOI wafer. In the bonding method, the device substrate on which an insulator is formed is bonded to the base substrate, and the device substrate is then thinly ground to form the SOI wafer. The SIMOX method has a disadvantage that it is difficult to control the thickness of the device substrate and generated defects in surface of the device substrate. Accordingly, the bonding method is typically used in the fabrication of the SOI wafer.
FIG. 1A through FIG. 1C are sectional views illustrating a method of fabricating a SOI wafer having a device formation layer by a prior bonding method. As shown in FIG. 1A, a device substrate 10 on which a first oxide film 11 is formed, and the first oxide film 11 is bonded by thermal oxidation to a base substrate 20 by a conventional method. As shown in FIG. 1B, the device substrate 10 is ground to the predetermined thickness, for example 9-12 .mu.m to form a Si layer 13. Then, the predetermined portions of the Si layer 13 are etched to expose the first oxide film 11, thereby forming trenches T. A second oxide film 14 is then uniformly deposited over the resultant by a CVD method and then patterned to be remained within the trenches T.
As shown in FIG. 1C, the remaining Si layer 13 is polished by a CMP method using the patterned second oxide film 14 as a polishing stopper to form a device formation layer 13-1, thereby fabricating a SOI wafer.
According to the prior art, in polishing the Si layer 13, a polishing pad of a polisher is contacted with the Si layer 13 and the second oxide film 14 which have a different polishing rates to cause the shaped of the pad to be deformed. Accordingly, in polishing the Si layer 13 and the second oxide film 14 at the same time, when the polishing pad contacts the second oxide film 14, the pressure applied to the polishing pad is concentrated to the second oxide film which has a lower polishing rate. Thus, the increased friction of the contact between the polishing pad and the second oxide film 14 causes the polishing pad to slow and stop, and the polishing of the Si layer to be automatically finished.
However, as the shape of the polishing pad is deformed during polishing of the second oxide film, dishing of the Si layer occurs wherein the Si layer is ground so as to be thinner in its central portion as shown in FIG. 1C. Accordingly, it is difficult to adapt the SOI wafer where dishing has occurred to the complete depletion type CMOS transistor that requires the thickness of the SOI wafer to be 1000 .ANG. within a precise range of .+-.10%. Furthermore, the process becomes complicated due to separate removal of the second oxide film used as a polishing stopper.